The present invention relates in general to semiconductor packaging, and in particular to package structures and methods of manufacture that are particularly suitable for radio frequency (RF) circuit applications.
The use of radio frequency (RF) amplifiers in, for example, wireless communication networks, is well known. With the considerable recent growth in the demand for wireless services, such as personal communication services (PCS), the operating frequency of wireless networks has increased dramatically and is now well into the gigahertz (GHz) frequencies. RF power amplification devices are used, e.g., in antenna base stations.
FIG. 1 shows a cross-sectional view of a portion of a conventional VDMOS (vertical diffused metal oxide semiconductor) package 220. The package 220 includes a semiconductor die 200 including source and gate regions (not shown) proximate the upper surface and a drain region (not shown) proximate the bottom surface. The semiconductor die 200 is disposed on top of a drain lead 202. A source contact layer 210 is connected to the source region and a gate 212 is in the die 200. A first wire 216 couples a source lead 206 to the source contact layer 210. A second wire 226 couples the gate 212 to a chip capacitor 214 that is used for impedance matching. A third wire 228 couples the chip capacitor 214 to a gate lead 204.
The semiconductor die 200 could alternatively comprise a bipolar RF transistor. For example, the base, emitter, collector, and the base of the bipolar RF transistor formed in the die 200 would respectively correspond to the source, drain, and gate of the VDMOS.
While the package shown in FIG. 1 is effective in some instances, a number of improvements could be made. For example, it would be desirable to reduce the source inductance in the device. Low inductance minimizes signal degradation, attenuation, and distortion.
It would also be desirable to increase the amount of heat that is removed from the package when it is in operation. RF power transistors generate a significant amount of heat. For example, 50% efficiency is not atypical of class A amplifiers. For high output power applications (e.g., more than 60 Watts), special packaging is required to facilitate the dissipation of heat from the power transistor to prevent overheating and further loss of efficiency. Overheating can also degrade the operational characteristics of a power transistor. For some applications, it is desirable to keep the temperature of the semiconductor die in an RF package to less than 100xc2x0 C. during operation.
It would further be desirable to address the above-noted problems, while enabling conventional input impedance matching.
Embodiments of the invention address these and other problems.
Embodiments of the invention are directed to semiconductor die packages and methods of making semiconductor die packages.
One embodiment of the invention is directed to a semiconductor die package comprising: a semiconductor die including a vertical power transistor, wherein the semiconductor die has a first surface and a second surface; a source electrode at the first surface of the semiconductor die; a gate contact region at the first surface of the semiconductor die; a drain electrode at the second surface of the semiconductor die; a base member, wherein the base member is proximate to the second surface of the semiconductor die and is distal to the first surface of the semiconductor die; and a cover disposed over the first surface of the semiconductor die, wherein the cover is coupled to the base member and is adapted to transfer heat away from the semiconductor die.
Another embodiment of the invention is directed to a semiconductor die package comprising: a semiconductor die comprising a vertical power transistor, wherein the semiconductor die has a first surface and a second surface; a source electrode at the first surface of the semiconductor die; a gate contact region at the first surface of the semiconductor die; a drain electrode at the second surface of the semiconductor die; a base member, wherein the base member is proximate to the second surface of the semiconductor die and is distal to the first surface of the semiconductor die; a first lead frame element electrically coupling the source electrode to the base member; a second lead frame element electrically coupling the gate contact region to the base member; and a joining structure coupled to at least the first or the second lead frame element.
Another embodiment of the invention is directed to a semiconductor die package comprising: a semiconductor die comprising a vertical diffused metal oxide semiconductor (VDMOS) RF power transistor, wherein the semiconductor die has a first surface and a second surface; a source electrode at the first surface of the semiconductor die; a gate contact region at the first surface of the semiconductor die; a drain electrode at the second surface of the semiconductor die; a base member comprising an insulated metal substrate, wherein the base member is proximate to the second surface of the semiconductor die and is distal to the first surface of the semiconductor die; a cover disposed over the first surface of the semiconductor die, wherein the cover is coupled to the base member and is adapted to transfer heat away from the semiconductor die; a plurality of securing members securing the cover to the base member; and a matching network coupled to the gate contact region.
Another embodiment of the invention is directed to a method for making a semiconductor die package, the method comprising: attaching a semiconductor die to a base member, wherein the semiconductor die comprises a vertical power transistor, a first surface, a second surface, a source electrode at the first surface of the semiconductor die, a gate contact region at the first surface of the semiconductor die, and a drain electrode at the second surface of the semiconductor die; and attaching a cover to the base member, wherein the cover is coupled to the base member and is adapted to transfer heat away from the semiconductor die.
Another embodiment of the invention is directed to a method for making a semiconductor die package, the method comprising: attaching a semiconductor die to a base member, wherein the semiconductor die comprises a vertical power transistor, a first surface, a second surface, a source electrode at the first surface of the semiconductor die, a gate contact region at the first surface of the semiconductor die, and a drain electrode at the second surface of the semiconductor die; attaching a first lead frame element to the source electrode and to the base member; attaching a second lead frame element to the gate contact region and to the base member; and attaching a joining structure to at least the first or the second lead frame element.
These and other embodiments can be described with reference to the foregoing Figures and Detailed Description.